Journal of Guangdong University of Technology ›› 2024, Vol. 41 ›› Issue (06): 20-25.doi: 10.12052/gdutxb.240029

• Integrated Circuit Science and Engineering • Previous Articles     Next Articles

A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier

Zheng Ji-wei1, Guo Chun-bing2   

  1. 1. School of Information Engineering, Guangdong University of Technology, Guangzhou 510006, China;
    2. School of Integrated Circuit, Guangdong University of Technology, Guangzhou 510006, China
  • Received:2024-02-29 Online:2024-11-25 Published:2024-12-31

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Abstract: In pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC), it is necessary to use large-open-loop gain operational amplifiers to improve the gain accuracy of closed-loop residual amplifications. The proposed ring amplifier uses a gain-enhanced output stage to improve the open-loop gain and stability, achieving an open-loop gain of over 90 dB and significantly reducing the residue gain errors without any calibration techniques, meeting the accuracy requirement of a 16 bit ADC. The ADC is implemented in the 65 nm CMOS process with an active area of 0.256 mm2. At a sampling rate of 25 MS/s and with Nyquist-rate input, the proposed ADC achieves simulated signal-to-noise distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 77.8 dB and 96.8 dB, respectively, with a power consumption of 2.8 mW. The proposed ADC achieves Walden and Schreier figure-of-merit (FoM) of 18.0 fJ/conversion-step and 174.3 dB, respectively.

Key words: pipelined-SAR ADC, ring amplifier, residue amplifier

CLC Number: 

  • TN453
[1] JIANG W, ZHU Y, CHEN C, et al. A 14b 500 MS/s single-channel pipelined-SAR ADC with reference ripple mitigation techniques and adaptively biased floating inverter amplifier [J]. IEEE Journal of Solid-State Circuits, 2023, 58(10): 2709-2721.
[2] WANG J C, KUO T H. A 72-dB SNDR 130-MS/s 0.8-mW pipelined-SAR ADC using a distributed averaging correlated level shifting ring amplifier [J]. IEEE Journal of Solid-State Circuits, 2022, 57(12): 3794-3803.
[3] LEE C C, FLYNN M P. A SAR-assisted two-stage pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 2011, 46(4): 859-869.
[4] WANG J C, HUNG T C, KUO T H. A calibration-free 14-b 0.7-mW 100-MS/s pipelined-SAR ADC using a weighted-averaging correlated level shifting technique [J]. IEEE Journal of Solid-State Circuits, 2020, 55(12): 3271-3280.
[5] KARANICOLAS A N, LEE H S, BARCRANIA K L. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 1993, 28(12): 1207-1215.
[6] LIU H C, LEE Z M, WU J T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration [J]. IEEE Journal of Solid-State Circuits, 2005, 40(5): 1047-1056.
[7] PARK Y, SONG J, CHOI Y, et al. An 11-b 100-MS/s fully dynamic pipelined ADC using a high-linearity dynamic amplifier [J]. IEEE Journal of Solid-State Circuits, 2020, 55(9): 2468-2477.
[8] HUANG H, XU H, ELIES B, et al. A non-interleaved 12-b 330-MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation [J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3235-3247.
[9] HERSHBERG B, WEAVER S, SOBUE K, et al. Ring amplifiers for switched capacitor circuits [J]. IEEE Journal of Solid-State Circuits, 2012, 47(12): 2928-2942.
[10] LAGOS J, HERSHBERG B P, MARTENS E, et al. A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers [J]. IEEE Journal of Solid-State Circuits, 2019, 54(3): 646-658.
[11] LIM Y, FLYNN M P. A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 2015, 50(12): 2901-2911.
[12] LIM Y, FLYNN M P. A 100 MS/s, 10.5 bit, 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers [J]. IEEE Journal of Solid-State Circuits, 2015, 50(10): 2331-2341.
[13] ZHANG X W, QIAN F Y, XI J X, et al. A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration [J]. Microelectronics Journal, 2022, 130: 105618.
[14] WU J, LI F, LI W, et al. A 14-bit 200MS/s low-power pipelined flash-SAR ADC[C]//2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) . Fort Collins, CO: IEEE, 2015: 1-4.
[15] HUNG T C, KUO T H. A 75.3-dB SNDR 24-MS/s ring amplifier-based pipelined ADC using averaging correlated level shifting and reference swapping for reducing errors from finite opamp gain and capacitor mismatch [J]. IEEE Journal of Solid-State Circuits, 2019, 54(5): 1425-1435.
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