用二维坐标下降法实现x=b/a的FPGA设计

广东工业大学学报 ›› 2011, Vol. 28 ›› Issue (1): 32-37.

用二维坐标下降法实现x=b/a的FPGA设计

广东工业大学 1.信息工程学院； 2.应用数学学院，广东广州 510006

出版日期:2011-12-25 发布日期:2011-12-25
作者简介:罗珍（1985-）,女，硕士研究生，主要研究方向为功率放大器的数字基带预失真、自适应算法

FPGA Design of the Dichotomous Coordinate Descent Algorithm for Complex Divider Problems

1.Faculty of Information Engineering;
2.Faculty of Applied Mathematics,Guangdong University of Technology,Guangzhou 510006,China

Online:2011-12-25 Published:2011-12-25

摘要/Abstract

摘要： 以二维坐标下降法（DCD算法）为基础，每次成功迭代后以二分之一的步长进行下一次迭代，使得它在解决线性方程时不仅保证了收敛度，并且实现了在FPGA（现场可编程门阵列）中无需用乘法器就可以计算出两个参数的比率，最后通过Matlab仿真验证了DCD算法在此应用中的可行性及其收敛速度快的特点.

关键词: DCD算法；步长；线性方程；参数比率；无需乘法器

Abstract: Based on the dichotomous coordinate descent (DCD) algorithm,having the next iteration with the power of half step size after a successful iteration guarantees the convergence speed when it solves the problem with the linear equations.It makes it possible to get the ratio of two numbers without multiplication on FPGA.MATLAB simulation is carried out to verify that the DCD algorithm has higher convergence speed in the application．

Key words: DCD algorithm; step size; linear equations; the ratio of two numbers; divider without multiplier

罗珍1, 刘海林2. 用二维坐标下降法实现x=b/a的FPGA设计[J]. 广东工业大学学报, 2011, 28(1): 32-37.

LUO Zhen1, LIU Hai-Lin2. FPGA Design of the Dichotomous Coordinate Descent Algorithm for Complex Divider Problems[J]. Journal of Guangdong University of Technology, 2011, 28(1): 32-37.

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