Abstract: The rapid scaling of semiconductor technologies has led to increasingly complex integrated circuit layouts, which pose severe challenges to maintaining manufacturing yield and highlight the urgent need for accurate lithographic hotspot detection. Existing detection methods are often constrained by limited layout modelling capacity, insufficient separability of augmented samples, and suboptimal classification performance. To overcome these challenges, a hotspot detection algorithm was developed that combined a multi-scale graph family modelling strategy with a hierarchical graph neural network. The proposed graph family model constructed both local subgraphs and a global graph to represent geometric details and contextual semantics simultaneously, thereby improving structural representation and preserving data separability under various augmentation operations. On this basis, a hierarchical GNN was designed to extract multi-level features and strengthen the model’s focus on critical core regions. Experimental evaluations on the ICCAD'19 TNSB benchmark demonstrate that the proposed method substantially improves data distribution balance, achieving a 206 percentage point increase in MNND and a 16 percentage point gain in Shannon entropy. Moreover, the detection model attains a recall of 99.91% with only a 1.12% false alarm rate, outperforming state-of-the-art alternatives. These results confirm that the proposed graph-based approach offers both strong structural expressiveness and robust detection capability, providing a promising solution for addressing the challenges of lithographic hotspot detection in advanced technology nodes.