Abstract: Based on a 40 nm complementary metal-oxide-semiconductor (CMOS) process, a wide dynamic range rectifier circuit chip is designed. The rectifier employs leakage current suppression and dynamic biasing techniques to enhance both power conversion efficiency (PCE) and input power dynamic range. A dynamic body-biasing technique is introduced, enabling P-type metal-oxide-semiconductor (PMOS) transistors to operate with a dynamically adjusted threshold voltage, thereby improving sensitivity and reducing reverse leakage current. A dedicated positive/negative voltage biasing network provides independent gate bias for each metal-oxide-semiconductor (MOS) transistor, adaptively generating bias voltages according to the input power level and further suppressing leakage under high-power conditions, which effectively extends the dynamic range. Additionally, a fully N-type metal-oxide-semiconductor (NMOS) leakage suppression structure is implemented at the input/output ports to reduce leakage current and enhance current drive capability. The core layout of the chip occupies an area of 94 μm × 80 μm. Measured results show that, at 900 MHz and with a 150 kΩ load, the rectifier achieves a peak PCE of 81.5%, and a dynamic range of 15.7 dB for PCE above 40%, representing a 6.7 dB improvement over conventional rectifier circuits.