Abstract: With the application scenarios of GNSS continuing to expand, its high energy consumption poses significant design challenges. As the most computation-intensive stage in the signal processing chain, GPS signal acquisition involves massive parallel code matching and sliding correlation operations, which impose significant challenges on hardware resources and power consumption. In this research, an analog in-memory computing (AIMC) architecture is introduced that leverages Resistive Random Access Memory (RRAM) crossbar arrays to execute code correlation in parallel. An array partitioning and overlapped accumulation strategy is employed to implement the GNSS long-code correlation. By dividing arrays, the output dynamic range is effectively compressed, thereby reducing the quantization precision requirement while saving hardware resources and power consumption. Furthermore, the computing-in-memory array exhibits strong reconfigurability, enabling flexible correlation length scheduling to support multiple navigation signals. Results demonstrate that the proposed architecture achieves a power consumption of 0.94 mW and an energy efficiency of 27.2 TOPS/W under 1 V supply. Compared with existing schemes, it offers superior acquisition accuracy, hardware efficiency, and robustness, making it highly suitable for low-power, high-performance GNSS receivers.