广东工业大学学报 ›› 2024, Vol. 41 ›› Issue (06): 20-25.doi: 10.12052/gdutxb.240029

• 集成电路科学与工程 • 上一篇    下一篇

基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器

郑基炜1, 郭春炳2   

  1. 1. 广东工业大学 信息工程学院, 广东 广州 510006;
    2. 广东工业大学 集成电路学院, 广东 广州 510006
  • 收稿日期:2024-02-29 出版日期:2024-11-25 发布日期:2024-12-31
  • 通信作者: 郭春炳(1971-),男,教授,博士,主要研究方向为模数混合集成电路设计,E-mail:cbguo@gdut.edu.cn
  • 作者简介:郑基炜(1999-),男,硕士研究生,主要研究方向为高精度模数转换器,E-mail:767621321@qq.com
  • 基金资助:
    广东省重点领域研发计划项目(2018B010115002)

A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier

Zheng Ji-wei1, Guo Chun-bing2   

  1. 1. School of Information Engineering, Guangdong University of Technology, Guangzhou 510006, China;
    2. School of Integrated Circuit, Guangdong University of Technology, Guangzhou 510006, China
  • Received:2024-02-29 Online:2024-11-25 Published:2024-12-31

HTML

48

PDF (PC)

127

摘要： 在高精度流水线逐次逼近型模数转换器(pipelined-SAR ADC)中，需要使用高开环增益的运算放大器来提高闭环级间残差放大器的增益精度。本文提出的环形放大器使用增益增强型输出级提高开环增益和稳定性，可以实现超过90 dB的开环增益，在不采用任何校准技术的情况下可以显著减小级间残差增益误差，满足16位ADC的精度要求。该ADC基于65 nm CMOS工艺设计，芯片面积为0.256 mm2。在25 MS/s的采样速率以及接近奈奎斯特频率输入信号的条件下，所设计的ADC仿真测得的信噪失真比(Signal-to-noise Distortion Ratio, SNDR)和无杂散动态范围(Spurious Free Dynamic Range, SFDR)分别为77.8 dB和96.8 dB，功耗为2.8 mW，品质因数FoMw和FoMs分别为18.0 fJ/ con.-step和174.3 dB。

关键词: 流水线逐次逼近型模数转换器, 环形放大器, 残差放大器

Abstract: In pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC), it is necessary to use large-open-loop gain operational amplifiers to improve the gain accuracy of closed-loop residual amplifications. The proposed ring amplifier uses a gain-enhanced output stage to improve the open-loop gain and stability, achieving an open-loop gain of over 90 dB and significantly reducing the residue gain errors without any calibration techniques, meeting the accuracy requirement of a 16 bit ADC. The ADC is implemented in the 65 nm CMOS process with an active area of 0.256 mm2. At a sampling rate of 25 MS/s and with Nyquist-rate input, the proposed ADC achieves simulated signal-to-noise distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 77.8 dB and 96.8 dB, respectively, with a power consumption of 2.8 mW. The proposed ADC achieves Walden and Schreier figure-of-merit (FoM) of 18.0 fJ/conversion-step and 174.3 dB, respectively.

Key words: pipelined-SAR ADC, ring amplifier, residue amplifier

中图分类号: 

  • TN453
[1] JIANG W, ZHU Y, CHEN C, et al. A 14b 500 MS/s single-channel pipelined-SAR ADC with reference ripple mitigation techniques and adaptively biased floating inverter amplifier [J]. IEEE Journal of Solid-State Circuits, 2023, 58(10): 2709-2721.
[2] WANG J C, KUO T H. A 72-dB SNDR 130-MS/s 0.8-mW pipelined-SAR ADC using a distributed averaging correlated level shifting ring amplifier [J]. IEEE Journal of Solid-State Circuits, 2022, 57(12): 3794-3803.
[3] LEE C C, FLYNN M P. A SAR-assisted two-stage pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 2011, 46(4): 859-869.
[4] WANG J C, HUNG T C, KUO T H. A calibration-free 14-b 0.7-mW 100-MS/s pipelined-SAR ADC using a weighted-averaging correlated level shifting technique [J]. IEEE Journal of Solid-State Circuits, 2020, 55(12): 3271-3280.
[5] KARANICOLAS A N, LEE H S, BARCRANIA K L. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 1993, 28(12): 1207-1215.
[6] LIU H C, LEE Z M, WU J T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration [J]. IEEE Journal of Solid-State Circuits, 2005, 40(5): 1047-1056.
[7] PARK Y, SONG J, CHOI Y, et al. An 11-b 100-MS/s fully dynamic pipelined ADC using a high-linearity dynamic amplifier [J]. IEEE Journal of Solid-State Circuits, 2020, 55(9): 2468-2477.
[8] HUANG H, XU H, ELIES B, et al. A non-interleaved 12-b 330-MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation [J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3235-3247.
[9] HERSHBERG B, WEAVER S, SOBUE K, et al. Ring amplifiers for switched capacitor circuits [J]. IEEE Journal of Solid-State Circuits, 2012, 47(12): 2928-2942.
[10] LAGOS J, HERSHBERG B P, MARTENS E, et al. A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers [J]. IEEE Journal of Solid-State Circuits, 2019, 54(3): 646-658.
[11] LIM Y, FLYNN M P. A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 2015, 50(12): 2901-2911.
[12] LIM Y, FLYNN M P. A 100 MS/s, 10.5 bit, 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers [J]. IEEE Journal of Solid-State Circuits, 2015, 50(10): 2331-2341.
[13] ZHANG X W, QIAN F Y, XI J X, et al. A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration [J]. Microelectronics Journal, 2022, 130: 105618.
[14] WU J, LI F, LI W, et al. A 14-bit 200MS/s low-power pipelined flash-SAR ADC[C]//2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) . Fort Collins, CO: IEEE, 2015: 1-4.
[15] HUNG T C, KUO T H. A 75.3-dB SNDR 24-MS/s ring amplifier-based pipelined ADC using averaging correlated level shifting and reference swapping for reducing errors from finite opamp gain and capacitor mismatch [J]. IEEE Journal of Solid-State Circuits, 2019, 54(5): 1425-1435.
No related articles found!
Viewed
Full text
127
HTML PDF
Just accepted Online first Issue Just accepted Online first Issue
0 0 0 0 0 127

  From Others local
  Times 39 88
  Rate 31% 69%

Abstract
169
Just accepted Online first Issue
0 0 169
  From local
  Times 169
  Rate 100%

Cited
Web of Science  Crossref   ScienceDirect  Search for Citations in Google Scholar >>
 
This page requires you have already subscribed to WoS.
  Shared   
  Discussed   
No Suggested Reading articles found!
版权所有 © 2017 《广东工业大学学报》编辑部
地址：广州市东风东路729号广东工业大学 邮编：510090
电话：020-37626653,020-37626139,020-37626396
邮箱：xbzrb@gdut.edu.cn
本系统由北京玛格泰克科技发展有限公司设计开发