广东工业大学学报 ›› 2024, Vol. 41 ›› Issue (06): 26-32.doi: 10.12052/gdutxb.240115

• 集成电路科学与工程 • 上一篇    

一种24~27 GHz共源共栅高增益低噪声放大器设计

陈鸿棋1, 罗德鑫2, 蓝亮1, 张志浩2, 章国豪2   

  1. 1. 广东工业大学 信息工程学院, 广东 广州 510006;
    2. 广东工业大学 集成电路学院, 广东 广州 510006
  • 收稿日期:2024-10-12 发布日期:2024-12-31
  • 通信作者: 章国豪(1964-),男,教授,博士,主要研究方向为微波、毫米波单片集成电路设计及新技术研究,E-mail:gz43811@qq.com
  • 作者简介:陈鸿棋(2000-),男,硕士研究生,主要研究方向为射频集成电路设计,E-mail:2112203095@mail2.gdut.edu.cn
  • 基金资助:
    国家重点研发计划项目(2018YFB1802100)；广东省“珠江人才计划”本土创新科研团队项目(2017BT01X168)

A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier

Chen Hong-qi1, Luo De-xin2, Lan Liang1, Zhang Zhi-hao2, Zhang Guo-hao2   

  1. 1. School of Information Engineering, Guangdong University of Technology, Guangzhou 510006, China;
    2. School of Integrated Circuits, Guangdong University of Technology, Guangzhou 510006, China
  • Received:2024-10-12 Published:2024-12-31

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摘要： 基于40 nm CMOS工艺，设计了一款高增益的低噪声放大器芯片。该芯片的拓扑架构采用了变压器输入匹配技术和正反馈同相放大技术，以提高输入匹配程度和增益。通过在传统共源共栅结构的输入级引入有源偏置网络及变压器匹配网络，实现的芯片在仿真环境下不仅能够在常温条件下稳定工作，还展现出–40 ℃~125 ℃范围内的优越性能。因此，该设计可用于不同温度环境下毫米波频段的收发机接收端口，并且有着一定的温度稳定特性。该低噪声放大器芯片的版图尺寸为0.383 mm×0.694 mm。版图后仿真结果显示，在24~27 GHz的工作频段内，该低噪声放大器常温下实现了低于4.96 dB的噪声系数、18.11 dB的最大增益、小于–16.08 dB的输入回波损耗和小于–11.54 dB的输出回波损耗。此外，该低噪声放大器设计还具有输入P1dB为–20.36 dBm、直流功耗Pdiss为12.8 mW等优异指标。

关键词: 高增益, 变压器输入匹配, 正反馈同相放大技术, 有源偏置网络

Abstract: Based on a 40 nm CMOS process, a high-gain low noise amplifier (LNA) chip was designed. The topology architecture of the chip adopted transformer input matching technology and positive feedback same-phase amplification technology to improve the input matching degree and gain. By introducing an active biasing network and a transformer matching network into the input stage of the traditional common-source common-gate structure, the chip can not only work stably at room temperature, but also shows excellent performance within the temperature range of –40 ℃ to 125 ℃ in simulation. Therefore, this design can be used for transceiver receiving ports in millimeter wave frequency bands under different temperature environments, and has certain temperature stability characteristics. The chip’s layout size is 0.383 mm×0.694 mm. The post-layout simulation results show that the LNA achieves a noise figure of less than 4.96 dB, a maximum gain of 18.11 dB, an input return loss of less than –16.08 dB, and an output return loss of less than –11.54 dB within the working frequency range of 24~27 GHz at room temperature. In addition, the LNA design has excellent performance indicators such as an input P1dB of –20.36 dBm and a DC power dissipation of 12.8 mW.

Key words: high-gain, transformer input matching, positive feedback same-phase amplification technology, active biasing network

中图分类号: 

  • TN492
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