Abstract: Solid State Disks based on 3D triple cell NAND flash has becoming a dominant storage medium in mass storage systems due to their high storage density and low cost per bit. With the rapid development of technologies, 3D NAND flash chips are becoming less reliable with high storage densities. Reduced reliability and overly conservative manufacturers' formulation of lifetime nominal values result in flash chips being prematurely phased out before reaching their actual lifespan with unnecessary waste. Lifetime prediction of flash chips through machine learning-based prediction models can optimize storage strategies to effectively extend lifetime and reduce losses. However, due to the differences in production processes, the error characteristics of flash memory chips are somewhat different from each other, which affects the accuracy of the life prediction of flash memory chips. In this paper, we experimentally find that the bit error rate of data retention errors can be used to characterize the number of program/erase cycles times, and propose to stimulate the interference between word-lines by writing specific contents to adjacent word-lines, which can effectively reduce the elapsed time and improve the accuracy of the life time prediction. Experimental results show that the elapsed time can be shorten by about 90.9%, and the prediction accuracy can be improved by 33.3 percentage points.

Key words: 3D NAND, life time predict, data retention error, word-line interference, SVM(Support Vector Machine)