Abstract: Physical verification is a critical concern in chip manufacturing, ensuring chip yield. Detecting potential hotspots in the chip layout before actual manufacturing is a critical step, which ensures manufacturing feasibility and enhances production efficiency. Traditional hotspot detection techniques suffer from long detection cycles and high computational resource consumption, resulting in increased time costs throughout the production cycle and limited detection of hotspot patterns. Based on active learning techniques and visual state space models, this paper proposes a new hotspot detection model. A memory-based sampling strategy is employed for query evaluation to mitigate the impact of the imbalance between hotspot and non-hotspot data on the model. Furthermore, the resolution constraints of the CNN structure and the secondary complexity of the ViT network architecture are optimized, leading to linear complexity for the hotspot detector. Testing results on the ICCAD-2012 competition dataset show that the proposed hotspot detector significantly reduces the false positive rate, achieving a rate of only 1.47%, while the recall reaches an impressive 98.89%.

Key words: hotspot detection, deep learning, visual state space model, active learning